1. Field of the Invention
This invention relates to computer systems, and more particularly to computer systems including interfaces for coupling to peripheral devices.
2. Description of the Related Art
Intelligent/Integrated drive electronics (IDE) is an interface technology for peripheral devices (e.g., disk drives) wherein the controller is integrated into the drive. AT attachment (ATA) is peripheral device interface standard which implements IDE. As a result, the two terms and their acronyms are often used interchangeably. Several versions of the ATA standard exist, including the basic ATA standard, ATA-2, ATA-3, and ATA-4. In addition, some organizations may refer to variations of the ATA standards by other names, including xe2x80x9cFast ATA,xe2x80x9d xe2x80x9cFast ATA-2, xe2x80x9d and xe2x80x9cUltra ATA.xe2x80x9d As used herein, the term xe2x80x9cAT Attachmentxe2x80x9d and the acronym xe2x80x9cATAxe2x80x9d refer to all variants of ATA and other interface standards implementing IDE.
The basic ATA standard (ANSI X3.221-1994) supports a single 16-bit parallel data channel which may be shared by two separate devices configured as master and slave. A typical personal computer includes two ATA interfaces (i.e., two ATA host adapters, which may integrated in a single chip) each providing a separate ATA data channel. Thus the typical personal computer is adapted for coupling to up to four different ATA devices.
Many different types of ATA devices are now available, including hard disk drives, CD-ROM drives, CD-R/W drives, and DVD drives. It is believed that with time more and more computer users will seek the ability to connect more than four ATA devices to a personal computer via ATA host adapter ports.
An existing solution for expanding ATA connectivity of a computer system is to add more ATA host adapters to the system (e.g., via plug in I/O cards). However, such added ATA host adapters are typically coupled to a single bus of the computer system (e.g., a peripheral component interface or PCI bus). Adding multiple ATA host adapters in this manner is typically not only costly, the multiple ATA host adapters can also significantly increase communication traffic on the bus to which they are coupled, consequently reducing system performance.
In addition, small computer system interface (SCSI) adapters and devices are readily available, and multiple SCSI storage devices can typically be coupled to a computer system via a single SCSI bus and adapter. However, SCSI components are typically more expensive than similar ATA components, and can be difficult to instill. For example, to add SCSI connectivity to a computer system, a SCSI adapter often must be installed in the system (e.g., via a plug in I/O card), and the associated driver software must be installed and configured.
It would thus be desirable to have a peripheral device interface (e.g., a host adapter) which may be configured to comply with an ATA standard. The host adapter would form an interface between a host system (e.g., a personal computer) and multiple ATA devices. The desired host adapter would allow more than two standard ATA devices to be coupled to the same ATA channel. Included in a personal computer, the desired host adapter would thus increase the ATA connection capabilities of the personal computer, allowing more than four relatively inexpensive standard ATA devices to be coupled to the personal computer.
Embodiments are described for accessing a group of peripheral devices, wherein the group of peripheral devices is one of multiple groups of peripheral devices. One of the embodiments includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system, and each group of peripheral devices receives a different group access signal.
The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register. The signal routing logic receives an access signal from the host system and routes the access signal to the group access signal for the group of peripheral devices selected by the value stored in the control register. The group access signal for each of the remaining groups of peripheral devices is deasserted so that the groups of peripheral devices not selected by the value stored in the control register are not accessed (i.e., do not respond to accesses from the host system).
Each of the peripheral devices may be a standard AT Attachment (ATA) device. In this case, the access signal may be, for example, an ATA chip select signal (e.g., the chip select 0 signal (CS0), or the chip select 1 signal (CS1)) or control signal (e.g., the data input/output read signal DIOR, or the data input/output write signal DIOW). Each of the peripheral devices may include multiple registers, and the group access signal may be used to select a portion of the registers of the peripheral devices of the selected group (e.g., a command register block or a control register block). The group access signal may be asserted in order to select the portion of the registers.
All of the peripheral devices may receive a common set of signals excluding the group access signals. For example, the peripheral devices of each group may be connected to a common data bus, and may receive the same data signals. The common data bus may be, for example, an ATA data bus.
The peripheral devices may be arranged to form, for example, p groups. The signal routing logic may include a 1-to-p demultiplexer coupled to the control register and configured to route the access signal from the host system to the selected group dependent upon the value stored in the control register.
In an ATA embodiment of the host adapter, the peripheral devices are standard ATA devices (e.g., ATA hard disk drives, ATA CD-ROM drives, ATA tape drives, or ATA DVD drives), and the host adapter may be an ATA host adapter that includes a control register and routing logic as discussed above. Each group of ATA devices is configured to receive an ATA chip select 0 (CS0) signal and an ATA chip select 1 (CS1) signal for controlling accesses from the host system to the ATA devices according to an ATA standard. A group of ATA devices may be a master/slave pair or a single device. The ATA host adapter includes the control register and signal routing logic described above. The control register stores a value for selecting one of the groups of ATA devices. The signal routing logic provides the CS0 and CS1 signals to the group of ATA devices selected by the value stored in the control register. The CS0 and CS1 signals for each of the remaining groups of ATA devices are deasserted so that the groups of ATA devices not selected by the value stored in the control register do not respond to accesses from the host system.
Each of the ATA devices includes multiple registers partitioned to form a control portion and a command portion. The CS0 signal is asserted in order to select the command portion, and the CS1 signal is asserted in order to select the control portion.
All of the ATA devices may receive common ATA signals excluding the CS0 and CS1 signals. For example, all of the ATA devices may be connected to a common ATA bus used to convey common ATA signals excluding the CS0 and CS1 signals.
The ATA devices may be arranged to form p groups, and the signal routing logic may include two 1-to-p demultiplexers. A first 1-to-p demultiplexer may be coupled to the control register and configured to route the CS0 signal to the ATA devices of the group selected by the value stored in the control register. The second 1-to-p demultiplexer may be coupled to the control register and configured to route the CS1 signal to the ATA devices of the group selected by the value stored in the control register.
One embodiment of a method for accessing a group of peripheral devices is described, wherein the group of peripheral devices is one of multiple groups of peripheral devices, and wherein each group of peripheral devices includes at least one peripheral device. Each group of peripheral devices receives a different group access signal for controlling access to the peripheral devices of the group. The method includes selecting the group of peripheral devices from among the multiple groups of peripheral devices. The selecting may include, for example, storing a value in a control register, wherein the value stored in the control register selects the group of peripheral devices from among the multiple groups of peripheral devices. The method also includes asserting an access signal, and routing the access signal to the groups of peripheral devices such that: (i) the asserted access signal is provided as the group access signal for the selected group of peripheral devices, and (ii) the group access signal received by the remaining groups of peripheral devices is deasserted. The routing may include, for example, routing the access signal to the group of peripheral devices selected by the value stored in the control register.
One embodiment of a method for accessing a group of ATA devices is described, wherein the group of ATA devices is one of multiple groups of ATA devices. The method includes storing a value in a control register for selecting the group of ATA devices from among the multiple groups of ATA devices. An ATA standard chip select 0 (CS0) signal and an ATA standard chip select 1 (CS1) signal are generated such that either the CS0 signal or the CS1 signal is asserted. The generated CS0 and CS1 signals are routed to the ATA devices dependent upon the value stored in the control register such that the generated CS0 and CS1 signals are provided to the ATA devices of the group selected by the value. The ATA devices of groups not selected by said value receive deasserted CS0 and CS1 signals such that the ATA devices of the non-selected groups do not respond to ATA accesses.